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CDB4352
Evaluation Board for CS4352
Features
Demonstrates Recommended Layout And Grounding Arrangements
Description
The CDB4352 evaluation board is an excellent means for quickly evaluating the CS4352 24-bit, high-performance stereo D/A converter. Evaluation requires an analog signal analyzer, a digital signal source, and a power supply. Analog line-level outputs are provided via RCA phono jacks. The CS8416 digital audio receiver IC provides the system timing necessary to operate the Digital-to-Analog converter and will accept S/PDIF and EIAJ-340-compatible audio data. The evaluation board may also be configured to accept external timing and data signals for operation in a user application during system development. ORDERING INFORMATION CDB4352
CS8416 Receives S/PDIF, & EIAJ-340Compatible Digital Audio
Headers for External PCM Audio
Requires Only a Digital Signal Source and Power Supplies for a Complete Digital-toAnalog Converter System
Evaluation Board
Hardware Switches
Clocks/Data Header S/PDIF Input (CS8416) Mux
CS4352
Analog Output (Line Level)
Muting
Reset Reset
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2006 (All Rights Reserved)
SEPTEMBER '06 DS684DB1
CDB4352
TABLE OF CONTENTS
1. CDB4352 SYSTEM OVERVIEW ............................................................................................................ 4 2. CS4352 DIGITAL-TO-ANALOG CONVERTER ..................................................................................... 4 3. CS8416 DIGITAL AUDIO RECEIVER .................................................................................................... 4 4. INPUT FOR CLOCKS AND DATA ......................................................................................................... 4 5. POWER SUPPLY CIRCUITRY ............................................................................................................... 4 6. GROUNDING AND POWER SUPPLY DECOUPLING .......................................................................... 5 7. HARDWARE CONTROL ........................................................................................................................ 5 8. ANALOG OUTPUT FILTERING ............................................................................................................. 5 9. PERFORMANCE PLOTS ....................................................................................................................... 6 10. DESIGN NOTE ................................................................................................................................... 11 11. SCHEMATICS .......................................................................... 12 12. REVISION HISTORY ......................................................................................................................... 21
LIST OF FIGURES
Figure 1. FFT (48 kHz, 0 dB) ...................................................................................................................... 6 Figure 2. FFT (48 kHz, -60 dB) ................................................................................................................... 6 Figure 3. FFT (48 kHz, No Input) ................................................................................................................ 6 Figure 4. FFT (48 kHz Out-of-Band, No Input) ............................................................................................ 6 Figure 5. 48 kHz, THD+N vs. Input Freq ..................................................................................................... 6 Figure 6. 48 kHz, THD+N vs. Level ............................................................................................................ 6 Figure 7. 48 kHz, Fade-to-Noise Linearity .................................................................................................. 7 Figure 8. 48 kHz, Frequency Response ...................................................................................................... 7 Figure 9. 48 kHz, Crosstalk ......................................................................................................................... 7 Figure 10. 48 kHz, Impulse Response ........................................................................................................ 7 Figure 11. FFT (96 kHz, 0 dB) .................................................................................................................... 7 Figure 12. FFT (96 kHz, -60 dB) ................................................................................................................. 7 Figure 13. FFT (96 kHz, No Input) .............................................................................................................. 8 Figure 14. FFT (96 kHz Out-of-Band, No Input) .......................................................................................... 8 Figure 15. 96 kHz, THD+N vs. Input Freq ................................................................................................... 8 Figure 16. 96 kHz, THD+N vs. Level .......................................................................................................... 8 Figure 17. 96 kHz, Fade-to-Noise Linearity ................................................................................................ 8 Figure 18. 96 kHz, Frequency Response .................................................................................................... 8 Figure 19. 96 kHz, Crosstalk ....................................................................................................................... 9 Figure 20. 96 kHz, Impulse Response ........................................................................................................ 9 Figure 21. FFT (192 kHz, 0 dB) .................................................................................................................. 9 Figure 22. FFT (192 kHz, -60 dB) ............................................................................................................... 9 Figure 23. FFT (192 kHz, No Input) ............................................................................................................ 9 Figure 24. FFT (192 kHz Out-of-Band, No Input) ........................................................................................ 9 Figure 25. 192 kHz, THD+N vs. Input Freq ............................................................................................... 10 Figure 26. 192 kHz, THD+N vs. Level ...................................................................................................... 10 Figure 27. 192 kHz, Fade-to-Noise Linearity ............................................................................................ 10 Figure 28. 192 kHz, Frequency Response ................................................................................................ 10 Figure 29. 192 kHz, Crosstalk ................................................................................................................... 10 Figure 30. 192 kHz, Impulse Response .................................................................................................... 10 Figure 31. System Block Diagram and Signal Flow .................................................................................. 12 Figure 32. CS4352 .................................................................................................................................... 13 Figure 33. Analog Outputs ........................................................................................................................ 14 Figure 34. PCM Input Headers ................................................................................................................. 15 Figure 35. CS8416 S/PDIF Input .............................................................................................................. 16 Figure 36. Power ....................................................................................................................................... 17 Figure 37. Silkscreen Top ......................................................................................................................... 18 2 DS684DB1
CDB4352
Figure 38. Top Side ................................................................................................................................... 19 Figure 39. Bottom Side ............................................................................................................................. 20
LIST OF TABLES
Table 1. System Connections .................................................................................................................... 5 Table 2. CDB4352 Jumper Settings .......................................................................................................... 11
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CDB4352 1. CDB4352 SYSTEM OVERVIEW
The CDB4352 evaluation board is an excellent means of quickly evaluating the CS4352. The CS8416 digital audio interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to supply external PCM clocks and data through a header for system development. The CDB4352 schematic has been partitioned into five schematics, as shown in Figures 32 through 36. Each partitioned schematic is represented in the system diagram shown in Figure 31. Notice that the system diagram also includes the interconnections between the partitioned schematics.
2. CS4352 DIGITAL-to-ANALOG CONVERTER
A description of the CS4352 is included in the CS4352 datasheet.
3. CS8416 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8416 Digital Audio Receiver, Figure 35. The outputs of the CS8416 include a serial bit clock, serial data, left-right clock, and a 128/256 Fs master clock. The CS8416 data format is fixed to IS. The operation of the CS8416 and a discussion of the digital audio interface is included in the CS8416 datasheet. The evaluation board has been designed such that the input can be either optical or coaxial, see Figure 35. However, both inputs cannot be driven simultaneously. Position 2 of S1 sets the output MCLK to LRCK ratio of the CS8416. This switch should be set to 256 (LO) for input Fs<=48 kHz and can be either 256 (LO) or 128 (HI) for Fs>48 kHz
4. INPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to external systems via the header J13. Header J13 allows the evaluation board to accept externally generated PCM clocks and data. The schematic for the clock/data input is shown in Figure 34. Switch position 1 of S1 selects the source as either CS8416 or header J13. Please see the CS4352 datasheet for more information.
5. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by three binding posts (GND, VL, and VA_H), see Figure 36. The VL supply can be jumpered to a +3.3 V regulator or provided externally through the VL binding post. VD and VA is normally supplied by the 3.3 V regulator but can be disconnected using J4 and J6 and then have external voltage applied to the VD and VA test points. The +5 V supply (which powers the regulators for this board) is normally supplied by a 5 V regulator but can be supplied externally by removing J7 and applying 5 V to TP8. Power consumption of the CS4352 can be measured through the voltage drop at J8, J9, J10, and J11 when the shunts are removed. WARNING: Refer to the CS4352 datasheet for maximum allowable voltages levels. Operation outside of this range can cause permanent damage to the device.
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CDB4352 6. GROUNDING AND POWER SUPPLY DECOUPLING
As with any high-performance converter, the CS4352 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 32 details the connections to the CS4352 and Figures 37, 38, and 39 show the component placement and top and bottom layout. The decoupling capacitors are located as close to the CS4352 as possible. Extensive use of ground plane fill in the evaluation board yields large reductions in radiated noise.
7. HARDWARE CONTROL
The CDB4352 is controlled through settings on switch S1. This allows for configuration of the board without a PC. A switch is provided for CS8416 MCLK speed, clock and data source for the board, and the hardware mode configuration of the CS4352.
8. ANALOG OUTPUT FILTERING
The analog output on the CDB4352 has been designed according to the CS4352 datasheet. This output circuit includes an AC coupling cap, the BJT mute circuit, and a single-pole R and C.
CONNECTOR
VL VA_H GND SPDIF INPUT - J16 SPDIF INPUT - OPT1 PCM INPUT - J13 AOUTA and AOUTB
INPUT/OUTPUT
Input Input Input Input Input Input Output
SIGNAL PRESENT
+ 1.5 V to +3.3 V power for the CS4352 serial interface +9 V to +12 V positive supply for the CS4352 high-voltage analog and the CDB4352 regulators Ground connection from power supply Digital audio interface input via coaxial cable Digital audio interface input via optical cable Input for master, serial, left/right clocks and serial data RCA line-level analog outputs
Table 1. System Connections
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CDB4352 9. PERFORMANCE PLOTS
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20 d B r A +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 1. FFT (48 kHz, 0 dB)
Figure 2. FFT (48 kHz, -60 dB)
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20 d B r A
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 50 100 200 500 Hz 1k 2k 5k 10k 20k
20k
40k
60k Hz
80k
100k
120k
Figure 3. FFT (48 kHz, No Input)
Figure 4. FFT (48 kHz Out-of-Band, No Input)
+0 -10 -20 -30 -40 d B r A -70 -80 -90 -100 -110 20 -50 -60 d B r A
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
50
100
200
500 Hz
1k
2k
5k
10k
20k
-100
-80
-60 dBFS
-40
-20
+0
Figure 5. 48 kHz, THD+N vs. Input Freq
Figure 6. 48 kHz, THD+N vs. Level
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CDB4352
+40 +35 +30 +25 +20 +15 +10 d B r A +1 +5 +0 -5 -10 -15 -20 -25 -30 -4 -35 -40 -140 -120 -100 -80 dBFS -60 -40 -20 +0 -5 20 -3 d B r A +2 +4 +5
+3
+0
-1
-2
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 7. 48 kHz, Fade-to-Noise Linearity
Figure 8. 48 kHz, Frequency Response
+0 -10 -20 -30
3 2.5 2 1.5
-40 1 -50 -60 d B -70 -80 -90 -100 -1.5 -110 -2 -120 -130 -140 20 -2.5 -3 0 V 500m 0 -500m -1
50
100
200
500 Hz
1k
2k
5k
10k
20k
500u
1m
1.5m sec
2m
2.5m
3m
Figure 9. 48 kHz, Crosstalk
Figure 10. 48 kHz, Impulse Response
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20 d B r A
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 11. FFT (96 kHz, 0 dB) DS684DB1
Figure 12. FFT (96 kHz, -60 dB) 7
CDB4352
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20 d B r A +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 50 100 200 500 Hz 1k 2k 5k 10k 20k
20k
40k
60k Hz
80k
100k
120k
Figure 13. FFT (96 kHz, No Input)
Figure 14. FFT (96 kHz Out-of-Band, No Input)
+0 -10 -20 -30 -40 d B r A -70 -80 -90 -100 -110 20 -50 -60 A d B r
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
50
100
200
500 Hz
1k
2k
5k
10k
20k
-100
-80
-60 dBFS
-40
-20
+0
Figure 15. 96 kHz, THD+N vs. Input Freq
Figure 16. 96 kHz, THD+N vs. Level
+40 +35 +30 +25 +20 +15 +10 d B r A +5 +0 -5 -10 -15 -20 -25 -30 d B r A
+5 +4
+3
+2
+1
+0
-1
-2
-3
-4 -35 -40 -140 -120 -100 -80 dBFS -60 -40 -20 +0 -5 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 17. 96 kHz, Fade-to-Noise Linearity 8
Figure 18. 96 kHz, Frequency Response DS684DB1
CDB4352
+0 -10 -20 -30 1.5 -40 1 -50 -60 d B -70 -80 -90 -100 -1.5 -110 -2 -120 -130 -140 20 -2.5 -3 0 V 500m 0 -500m -1 3 2.5 2
50
100
200
500 Hz
1k
2k
5k
10k
20k
250u
500u
750u sec
1m
1.25m
1.5m
Figure 19. 96 kHz, Crosstalk
Figure 20. 96 kHz, Impulse Response
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20 d B r A
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 21. FFT (192 kHz, 0 dB)
Figure 22. FFT (192 kHz, -60 dB)
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20 d B r A
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 50 100 200 500 Hz 1k 2k 5k 10k 20k
20k
40k
60k Hz
80k
100k
120k
Figure 23. FFT (192 kHz, No Input) DS684DB1
Figure 24. FFT (192 kHz Out-of-Band, No Input) 9
CDB4352
+0 -10 -20 -30 -40 d B r A -70 -80 -90 -100 -110 20 -50 -60 A -70 -80 -90 -100 -110 -120 d B r +0 -10 -20 -30 -40 -50 -60
50
100
200
500 Hz
1k
2k
5k
10k
20k
-100
-80
-60 dBFS
-40
-20
+0
Figure 25. 192 kHz, THD+N vs. Input Freq
Figure 26. 192 kHz, THD+N vs. Level
+40 +35 +30 +25 +20 +15 +10 d B r A +5 +0 -5 -10 -15 -20 -25 -30 -35 -40 -140 -120 -100 -80 dBFS -60 -40 -20 +0
d B r A
+5 +4
+3
+2
+1
+0
-1
-2
-3
-4
-5 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 27. 192 kHz, Fade-to-Noise Linearity
Figure 28. 192 kHz, Frequency Response
+0 -10 -20 -30
3 2.5 2 1.5
-40 1 -50 -60 d B -70 -80 -90 -100 -1.5 -110 -2 -120 -130 -140 20 -2.5 -3 0 V 500m 0 -500m -1
50
100
200
500 Hz
1k
2k
5k
10k
20k
200u
400u sec
600u
Figure 29. 192 kHz, Crosstalk 10
Figure 30. 192 kHz, Impulse Response DS684DB1
CDB4352
JUMPER / SWITCH
J7 J4 J5 J6 J8 J9 J10 J11 S1 S2 J12 J17
PURPOSE
Selects source of voltage for the +5V supplies Selects source of voltage for the VD supplies Selects source of voltage for the VL supply Selects source of voltage for the VA supply Current measure for VD Current measure for VL Current measure for VA Current measure for VA_H Sets clock source, CS8416 clock speed, and CS4352 settings Reset Mute Disable
POSITION
+5 V *+5V_REG VD *+3.3V REG VL *+3.3V REG VA *+3.3V REG *shunted *shunted *shunted *shunted *1 = open *2, 3, 4, 5 = closed *LED MUTE
FUNCTION SELECTED
Voltage source is +5 V test point (TP8) Voltage source is +5 V regulator Voltage source is VD test point (TP2) Voltage source is +3.3 V regulator Voltage source is VL binding post Voltage source is +3.3 V regulator Voltage source is VA test point (TP7) Voltage source is +3.3 V regulator When shunt is removed, the voltage can be measured across a fixed resistance to determine current. When shunt is removed, the voltage can be measured across a fixed resistance to determine current. When shunt is removed, the voltage can be measured across a fixed resistance to determine current. When shunt is removed, the voltage can be measured across a fixed resistance to determine current. position 1: 0 = external clock source, 1 = CS8416 position 2: 0 = 8416 MCLK is 256xFs, 1 = 128xFs Position 3,4,5: see CS4352 datasheet Enables reset for CS4352 and CS8416 when pressed Bypasses muting to turn on LED Normal muting circuit
Table 2. CDB4352 Jumper Settings
*Default Factory Settings.
10.DESIGN NOTE
10.1 CDB4352 Revision A.0
D2 has been removed and shorted and R2 has been removed. The serial audio decode table for S1 is incorrect. `01' should be RJ-24 and `10' should be LJ The polarity of the silkscreen for Z1, Z2, Z3, Z4, and Z5 is incorrect The CS4352 revision is A1
10.2
CDB4352 Revision B.0
No errors at this time
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11.SCHEMATICS
Hardware Switch Figure 34 Reset Circuit
Power Figure 36
8416 Digital Audio Receiver Figure 35
MCLK SCLK LRCK SDIN
CS4352 Figure 32
Channel A Outputs and Mute Figure 33 Channel B Outputs and Mute Figure 33
PCM Inputs
Figure 34
Figure 31. System Block Diagram and Signal Flow
CDB4352
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Figure 32. CS4352
CDB4352
13
14
CDB4352
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Figure 33. Analog Outputs
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CDB4352
Figure 34. PCM Input Headers
15
16
CDB4352
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Figure 35. CS8416 S/PDIF Input
CDB4352
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Figure 36. Power
17
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CDB4352
Figure 37. Silkscreen Top
18
19
CDB4352
Figure 38. Top Side
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CDB4352
Figure 39. Bottom Side
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CDB4352 12.REVISION HISTORY
Release
DB1 DB2 Initial Release Added Performance Plots
Changes
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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